In recent years, progressive research and development has been conducted on nonvolatile memory devices including memory cells for which variable resistance elements are used. A variable resistance element is an element which has a property that its resistance value reversibly changes according to an electrical signal and which can store data corresponding to the resistance value in a nonvolatile manner.
Commonly known as a nonvolatile memory device including variable resistance elements is a nonvolatile memory device, referred to as a so-called 1T1R cross point memory, in which memory cells are arrayed in a matrix. In the 1T1R cross point memory, memory cells each including a transistor and a variable resistance element connected in series are provided at cross-points of orthogonally arranged bit lines and word lines.
Furthermore, a nonvolatile memory device aiming at higher integration, referred to as a so-called 1D1R cross point memory, is also known in which memory cells are arrayed in a matrix. In the 1D1R cross point memory, memory cells are provided at cross-points of orthogonally arranged bit lines and word lines. Each memory cell includes a bidirectional diode element functioning as a current steering element and a variable resistance element connected to the bidirectional diode element in series. Also known is a nonvolatile memory device including layers of memory cells of the 1D1R cross point memory. Conventionally, various methods have been proposed for writing in memory cells of such nonvolatile memory devices including variable resistance elements.
Patent Literature 1 (PL1) discloses, regarding the memory cells of a 1D1R cross point memory, a method of applying voltage to the word lines and bit lines in an initial breakdown operation, which is an operation of initializing the memory cells. FIG. 20 shows the configuration of the memory cell array of the nonvolatile memory device disclosed in PL1. FIG. 21 shows the waveforms of voltages applied to a selected word line, unselected word lines, selected bit lines, unselected bit lines at the time of performing the initial breakdown on the memory cell array.
The nonvolatile memory device of PL1 applies a selected voltage (VSS in FIG. 21) to the selected word line, and at the same time, places a plurality of selected bit lines in floating state. This reduces each of the voltages at the bit lines to which memory cells for which the initial breakdown has finished are connected. With this, stable initial breakdown is ensured even when the time lengths of the initial breakdown vary among the bits.
Patent Literature 2 (PL2) discloses a method of determining a writing order in the operation of writing in memory cells of a 1R cross point memory. FIG. 22 shows the configuration of the memory cell array of the nonvolatile memory device disclosed in PL2. FIG. 23 shows an order of memory cells, in the memory cell array, in which writing is performed.
As for the method of PL2, when unselected memory cells provided on the same line as a selected line include many memory cells in the high resistance state and when the resistance of such memory cells is to be decreased, writing starts from the memory cell farthest from the drive circuit. Furthermore, with this method, when there are many memory cells in the low resistance state on the same line and when the resistance of such memory cells is to be increased, writing starts from the memory cell nearest to the drive circuit. This method suppresses the adverse effect of leak current, prevents a decrease in the writing speed, and simplifies the control over the resistance values after writing.